 Verific Design AutomationCompany Description:Verific Design Automation was founded in 1998 by EDA industry veteran Rob Dekker. Prior to founding Verific, Dekker was a Software Developer, Manager, and Director at Exemplar Logic where he was the architect and a primary developer of Leonardo, Exemplar's flagship synthesis product which has sold over 10,000 copies to date. Verific's Board of Directors include Ewald Detjens, founder of Exemplar Logic, and Bob Gardner, who has held president and COO positions at several succesful startups.Verific Design Automation Inc. develops and sells source code (C++) Verilog and VHDL front-ends (parsers, analyzers, elaborators) as well as a generic hierarchical netlist database for EDA applications. Many EDA and semiconductor companies worldwide are shipping products incorporating Verific's Verilog and VHDL technology, with a combined customer base of over 30,000 users. Applications include FPGA synthesis, Model Checking, Functional Verification, Hardware Acceleration, RTL Debug, Logic Equivalence Checking, RTL Floorplanning, HDL Entry, and Design for Test. Worldwide Headquarters:
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