IP-Tape

Company:

Dynamic Engineering

Description:

The IndustryPack compatible IP-Tape design adds 48 digital parallel IO lines to one slot of your carrier board. The IO is dedicated to a DTC interface. Other interfaces can be implemented. The DTC interface has 22 Address, 16 Data plus Parity, 4 control and 5 status lines. Parity is automatically generated in write mode and checked in read mode. Parity is programmable to be old or even. Outputs in "tape" mode are driven with 64 mA open-drain devices. A 470 ohm pull-up resistor is provided on board. The registers are mapped as 16 bit words and are read-writeable. The Timing can be altered with a change to the state-machine for other implementations. The state machine has counters to create the delays for each state. In this design, the counters are set to wait 4.5 uS after address is asserted to assert Address Enable [ENABLEn], then 1.5 uS before asserting Data Enable [DTC_ENA]. RW is asserted with ENABLEn. RW is high as a default and for read accesses. RW is asserted low for a write cycle. The Global enable [DTC_DECn] is asserted at the start of the cycle. The IP-Parallel-Tape and its engineering kit are now available for ordering

Send in your specifications and we can quote a custom version for you. Sales@dyneng.com (831) 336-8891.

Product Properties

• OSes supported:
  VxWorks,VxWorks,Windows XP,Linux,C-Source code,C-Source code,Application Examples
• URL to the product/service/project description on company's website:
  http://www.dyneng.com/ip_par_tape.html