PC104p4IP

Company:

Dynamic Engineering

Description:

If you want to use IndustryPack¨ modules with your PC/104+ system then the PC104p4IP is the choice for you. The PC104p4IP combines features you need with simplicity and speed. Up to 4 IP modules can be installed. 32 bit and double wide modules fit right in. Each slot has independent operation - control, clocking, IO, power filtering and protection. The PC104p4IP is highly integrated with the PCI and IP interfaces closely coupled within the same FPGA. As a result the PC104p4IP is faster, has a higher MTBF, and is easier to use than competing designs. There are fewer initialization steps and fewer PCI addresses to deal with and yet there are more features to work with. With the Windows¨XP driver; operation can be "plug and play".
Our customers are our best source of feed-back and new ideas to implement. The PC104p4IP is now revision A for the PROM. The new features include Byte and Word Swapping, Bus error status for each slot independently, and 32 IP support. Shipping now. If you have PC104p4IPs and want to update to the latest firmware we have a PROM update program. A minimal cost of $25 for the first updated PROM. Please provide your serial number(s) to be updated along with your PO.
Multi-board operation is supported. With multiple PC104p4IPs in your system and unique cabling, sensors etc. for each slot on each PC104p4IP it is important to "know" which PC104p4IP is which and to properly control the IP modules mounted to them. A surface mount "dip switch" is provided which provides an identifier to the software. A specific PC104p4IP can be matched up with the PCI address allocated to make for deterministic control. The switch can also be used for other purposes; configuration control or debugging for example. The switch values are available to be read via the PCI bus.
Each slot has a separate clock controller for 8 and 32 MHz operation. The clocks are locked together for the four slots plus the state-machine. Glitch free operation means the frequency can be be changed on the fly. Series and parallel terminations with equal length traces insure clean clocks and coherant operation across the 4 IPs and the controlling state-machine. A well designed clock distribution is critical for reliable operation.