Index Dedicated Systems Magazine 01q2
Editorial
By Martin Timmerman, Chief-Editor of Dedicated Systems
Magazine, Dedicated Systems Experts.
CHIPS ISSUE - 01q2 - p. 3
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| CO-DESIGN |
Getting Hardware and Software to Speak the Same
Language
By providing an industry standard language that can be
used for system, hardware and software design, SystemC is enabling systems,
hardware and software teams to “speak ” the same language. This means much
better communications between the groups.It also means that, as the software
and hardware are developed, they can be simulated against the system specification
so any design problems can be resolved much earlier in the design process.
In today ’s world of multi-national design efforts,one
language for system-level design is imperative. If someday some group manages
to develop the world ’s ideal system-level design language, then it can
be considered for adoption. Meanwhile, everyone is trying to deal with
the complexity of today ’s designs.SystemC will go a long way towards shortening
the time it takes to get good system-level design tools to market. SystemC
will also provide a common language for IP model exchange, which is essential
as well.
By Pete Hardee, Director of Product Marketing, CoWare,Inc.
CHIPS ISSUE - 01q2 - p. 6 
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Exploration of Hardware/Software Design Space in the Co-design Process
Analysis methods based on estimation to approximate a
priori the system performance/cost can play an important role in hardware/software
co-design of real time systems. This paper presents a fast analysis approach
for exploration of hardware/software design space. This approach is based
mainly on synthesis and simulation results and guided by estimation of
costs and performances.
Estimation models are introduced in order to evaluate
cost/performance for a given hardware/software solution. A study in applying
the environment to the development of a real time robot arm controller
is then described. The results show fast convergence of estimated to real
solution.
By Mohamed ABID, Electrical Engineering Department,
Ecole Nationale d'Ingenieurs de Sfax.
CHIPS ISSUE - 01q2 - p. 10
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| DEBUGGING & TESTING |
Evaluation of a New Emulation Port Using an M-CORE
Architecture System
A new standard for real-time emulation is being developed
by a consortium of companies including Motorola, Siemens, Hitachi, STM,
tas and Hewlett Packard. Officially named the Global Embedded Processor
Debug Interface Standard Consortium, this group of technical and business
professionals is addressing the rigorous challenges encountered daily by
design engineers who develop complex real-time systems.
The goal of this consortium is to define a general-purpose
specification which describes a common set of microcontroller on-chip debug
features, protocols, pins and interfaces to external tools which may be
used by real-time embedded control application developers. The consortium
was started in late 1997 and has met on several occasions as well as conducted
numerous conference calls to develop the current proposed specification
for standard with intentions to pass this specification to the Institute
of Electrical and Electronic Engineers (IEEE) for development as an IEEE
standard. The project has been code named Nexus and will be referenced
as such in this paper.
By David Ruimy Gonzales, Senior Member of Technical
Staff, Motorola Embedded Platform Solutions Center.
CHIPS ISSUE - 01q2 - p. 17
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Manual and Automatic VHDL/Verilog Test Bench
Coding Techniques
One of the most time consuming
tasks for users of HDL languages is coding test benches to verify the operation
of their design. In his book "Writing Testbenches", Janick Bergeron estimates
that 70%of design time is spent verifying HDL code models and that the
test bench makes up 80%of the total HDL code generated during product development.
In this paper we propose the use of automatic code generation tools to
reduce the time required to create and maintain test benches.In particular,
we will discuss TestBencher Pro an automatic code generation tool for VHDL
and Verilog test benches.
By Donna Mitchell, is vice president
of strategic marketing, SynaptiCAD Inc.
CHIPS ISSUE - 01q2 - p. 27
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| NETWORKING |
OMAP ™:Enabling Multimedia Applications in Third
Generation (3G)Wireless Terminals
This paper describes how the Open Multimedia Applications
Platform ™ software and hardware architecture enables multimedia applications
in third-generation (3G) wireless appliances. It provides an overview of
OMAP ™ strategy, concepts, main milestones, and achievements. It also describes
OMAP hardware architecture, explains how multimedia applications can benefit
from this advanced architecture, and why a RISC/DSP approach is superior
to RISC-only architecture.
This paper outlines OMAP software concepts to show how
an architecture that combines two heterogeneous processors (RISC and DSP),
several operating system (OS)combinations, and applications running on
both DSP and RISC can be made accessible seamlessly to third parties.
The final parts of the paper outline how key multimedia
applications such as speech and video can be integrated in an OMAP solution.
By Jamil Chaoui, OMAP Program Manager, Texas Instruments.
CHIPS ISSUE - 01q2 - p. 34
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Solano ™Communications IC: A High-Throughput
Solution for 3G Wireless and Broadband Base Stations
This article contains perspectives on optimizing Digital
Signal Processing through software-driven wideband wireless architecture
overview. As demand for third-generation (3G) wireless systems increases
rapidly throughout the coming decade, the need for higher bandwidth will
require ever-increasing signal processing and base station flexibility.
These advances, in turn, will depend on flexible software radio architectures
and on enhancements at the processing chip level.
By Lee Pucker, Chief Engineer,Wireless Systems, Spectrum
Signal Processing Inc.
CHIPS ISSUE - 01q2 - p. 40
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Network Processors and their Impact on Real-time Operating Systems
Network usage is growing exponentially, pushing existing
communications infrastructure to their performance and capacity limits.
Communications product development cycles are beginning to take longer
than the service life of the equipment being developed. Network processor
technology promises shortened development cycles, greater flexibility,
and longer product service life. The truly amazing part of this revolution
is that everyone seems to be overlooking the impact network processor technology
has on today's real-time operating systems. In the sections that follow,
we'll look at network processor technology and new requirements network
processors place on a real-time operating system.
By Curtis A.Schwaderer, Director of Network Technologies,
Microware Systems Corporation.
CHIPS ISSUE - 01q2 - p. 44
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Home Networking Using Phoneline Wiring
Until recently, home networks depended on special cables
(typically requiring professional installation) to link PCs, audio-video
equipment and peripheral devices together, which could be expensive and
problematic if the hardware components were in different rooms of the house.
Thanks to recent technological developments, consumers
can use their already installed telephone wiring systems to link multiple
computers and digital appliances around the house.
This article examines the key phoneline technology that
promise to deliver the holy grail of home networks without the need to
run hundreds of meters of new data cables inside the walls of households.
By Amit Dhir, Xilinx Corporation.
CHIPS ISSUE - 01q2 - p. 52
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| SOC |
Virtual Machine Technology: Managing Complexity
and Providing Portability for Embedded Systems
IBM's VisualAge for Embedded Systems Virtual Machine
provides an independent Virtual Machine that is both designed to be compatible
with the Java Virtual Machine standard and developed from the ground up
for embedded system applications. Using a Virtual Machine, such as VisualAge,
provides embedded developers with the tools needed to design and build
devices with communications facilities, to download and run applications
and new platform components, while maintaining compatibility with the Java
platform. Designing to a Virtual Machine reduces the complexity of porting
to other processors and hardware devices, and can improve time to market
now and for future releases. This article gives you the details.
By Kim Clohessy, CEO, Object Technology,Inc.
CHIPS ISSUE - 01q2 - p. 58
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Integration of Complex Mixed-Signal Solutions onto System on a Chip
Analysts predict that by the year 2005, over 70%of new
system-on-a-chip designs will have mixed-signal content. To successfully
meet this growing demand for integrated mixed-signal functionality on complex
ASICs, semiconductor companies must address topics ranging from the process
technology definition to tightly coupled tools and methodology for both
ASICs and mixed-signal core development.
This paper discusses the importance of mixed-signal methodology
as a tool for SoC, the limitations and solutions, and provides a silicon
example of mixed-signal CMOS system-on-a-chip.
By Marco Mariani, Mixed Signal Marketing Manager, LSI
Logic Europe.
CHIPS ISSUE - 01q2 - p. 61
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System-on-Chip Designs: Strategy for Success
System-on-chip has been a nebulous term, that mystically
holds out a lot of excitement, and has been gaining momentum in the electronics
industry. While the potential is huge, the complexities are several, and
countering these to offer successful designs is a true engineering challenge.SoC
design and validation demands certain measured approaches.Following are
what we call the Five Guiding Principles of SoC design.
By Udaya Kamath &Rajita Kaundin, Wipro Technologies.
CHIPS ISSUE - 01q2 - p. 64
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| CPCI |
High-availability Computing in an Open Systems World
High-Availability Computing and Open Systems have been
concepts in conflict for years. The vast majority of applications for Open
Systems do not require "5-nines" availability (systems available 99.999%
of the time, implying no more than 5 minutes of down time per year). Thus,
the design points for industry standard open systems emphasise other priorities
- notably cost - over non-stop availability. Many telecom and internet
applications, meanwhile, demand high-availability. This has led to the
creation of numerous proprietary computing solutions for telecommunications.
By David McKinley, Director of Engineering-High Availability,
RadiSys Corporation.
CHIPS ISSUE - 01q2 - p. 69
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CompactPCI IP Backplane Standard Proposed for Next-Gen Network Needs
The constant challenge for designers of high-availability
and next-generation IP-telephony systems for competitive carriers is building
systems increasingly more dependable, smaller and cheaper to own and use.
Though still in wide use, first-generation solutions are no longer sufficient.
Things improved significantly with second-generation architecture taking
advantage of the CompactPCIÒ form factor. But even that has limitations.
Compact Packet Switching Backplane (cPSB) now emerges as a far more efficient
network architecture. Its technological value can best be appreciated by
overviewing this design progression.
By Hank Heneghan, Senior Product Manager, Performance
Technologies,Inc.
CHIPS ISSUE - 01q2 - p. 76
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| VARIOUS |
FPGA Solution for Low Cost Applications of Real-Time Automated Visual
Inspection (RT-AVI)Systems
Real-time requirements set an important aspect to consider
during the design of most automated systems for visual inspection tasks.
Usually, it is necessary to use specialised hardware to satisfy the above
requirements. During the development stage it is normal to use expensive
hardware that provides more and higher functionality than the necessary
in the final application. This paper presents a hardware solution for low
cost applications of Real-Time Automated Visual Inspection (RT-AVI) systems.
This includes a new methodology for development of hardware cores implemented
on programmable logic devices (FPGA). The proposed solution have been applied
to different industrial inspection systems.In particular, the architecture
has been implemented for SMARTMEC AVI system within a RENAULT VI crankshaft
production line and also reused for the development of the SIVAFRUT AVI
system for the quality inspection of preserved orange segments.
By A.Iborra,C.Fernández, B.Álvarez and
J.M.Fernández-Meroño, DSIE.Universidad Politécnica
de Cartagena.
CHIPS ISSUE - 01q2 - p. 79
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Serial Busses Take Over
Low Voltage Differential Signaling (LVDS) connections
have been gaining in popularity over the last few years. They address many
of the performance restrictions inherent in traditional parallel bus designs.
By Stephen Paavola, Product Manager, SkyComputers,Inc.
CHIPS ISSUE - 01q2 - p. 85
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Bringing 64bit UltraSPARC computing to the embedded world
The UltraSPARC IIe was developed to meet the specific
needs of embedded 64-bit high-end embedded computing. The processor is
designed to deliver impressive throughput in a highly integrated package
with the right balance of power consumption to facilitate compact, low
cost system design. This articles explains how this is possible.
By Peter Palm, Group Marketing Manager, Sun Microsystems.
CHIPS ISSUE - 01q2 - p. 87
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LVDS in Harsh Environments with the Next Generation Receivers from
Texas Instruments
TI has developed the next generation of TIA/EIA-644 low
voltage differential signaling (LVDS) receivers for operation in noisy
and harsh environments. Because of the reduced common-mode voltage range
dictated by the 644 standard, LVDS was unsuitable in some applications
as a replacement for the long established standards like RS485 and RS422.
TI has addressed this concern by releasing a series of receivers with improved
ground noise tolerance, making TI's next generation receivers suitable
for these more rugged applications. This document describes the following:
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How common-mode noise is generated and how it affects the
transmission system.
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Which noise margins exist in the transmission systems available
today.
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What the test results prove.
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The benefits of the next generation LVDS receivers SN65LVDS32A,
SN65LVDS3486A and SN65LVDS9637A, which are also available as SN65LVDT with
an integrated 110 W termination.
By Ludo de Graaf, Digital Signal Processing Solutions,
Texas Instruments.
CHIPS ISSUE - 01q2 - p. 90
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| EC |
EU SUPPORT FOR ADVANCED SIGNAL PROCESSING
SYSTEMS AND APPLICATIONS
By Javid Khan, Scientific Officer, Directorate General
Information Society European Commission.
CHIPS ISSUE - 01q2 - p. 94
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| RT-DOCTOR |
| Using UML to Design an Embedded System Introduction
By Alan Moore, Vice President of Product Strategy,
ARTiSAN Software Tools,Inc.
CHIPS ISSUE - 01q2 - p. 95
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CHIPS ISSUE - 01q2 - p. 98
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CHIPS ISSUE - 01q2 - p. 104
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CHIPS ISSUE - 01q2 - p. 113
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