Index Real-Time Magazine 2Q99
Editorial
By Martin Timmerman, Chief-Editor of Real-Time Magazine,
Real-Time Consult.
DSP TECHNOLOGY - 99q2 - p. 3
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| RTOS EVALUATIONS |
RTOS Market Overview - A Follow up
In the previous issue, some preliminary results of our
market survey have been published. At that time,
1300 samples were available for the survey. Today we
count 2360 samples. This means that all
these people registered to have access to the visitor’s
centre in our website. (http://www.dedicated-systems.com)
If you did not register yet, don’t hesitate to do so
and take profit of the FREE Windows-NT workstation
evaluation and “What makes a good RTOS” reports. With
the additional 1000 samples, we can now go
in some details about the differences in tendencies between
North America, Europe and the rest of
the world.
By Martin Timmerman, President & CEO, Real-Time
Consult.
DSP TECHNOLOGY - 99q2 - p. 6
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INTIME 1.20 Evaluation - Executive Summary
The following article is the executive summary report
of the evaluation of INtime 1.20, the real-time extension to Windows NT
from Radisys Corporation Ltd. It gives an overview of the system architecture,
API richness, performance and available support.
By Martin Timmerman, Chief-Editor of Real-Time Magazine,
Bart Van Beneden, Project Manager, Real-Time Consult.
DSP TECHNOLOGY - 99q2 - p. 9
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HYPERKERNEL 4.3 Evaluation - Executive Summary
The following article is the executive summary report
of the evaluation of Hyperkernel 4.3, the real-time extension to Windows
NT from Imagination Systems Inc. It gives an overview of the system architecture,
API richness, performance and available support.
By Martin Timmerman, Chief-Editor of Real-Time Magazine,
Bart Van Beneden, Project Manager, Real-Time Consult.
DSP TECHNOLOGY - 99q2 - p. 14
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RTOS Evaluations - Latest news
In the sumer of 1998, Real-Time Consult launched an RTOS
evaluation program. This paper contains the latest developments in this
project.
By Martin Timmerman, Chief-Editor of Real-Time Magazine,
Bart Van Beneden, Project Manager, Real-Time Consult.
DSP TECHNOLOGY - 99q2 - p. 19
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| MARKET |
Virtual components in the DSP world
This paper presents state of the art of DSP virtual components
(IPs) available on the market according
to the author’s best knowledge. These cores are firstly
analysed according to the technology on which
they have been qualified. Most of the IPs are today qualified
on at least one technology (ASIC or
FPGA). Statistics are proposed according to the type
of validation technology. Secondly, an analysis is
made concerning the type of DSP cores ranging from filters
to sophisticated multiprocessors and sta-
tistical distribution is shown. Thirdly, Comments on
the set of 32 providers are made according to their
offer. Finally, IP description and deliverable issues
are mentioned.
By Gabriele Saucier, Professor at the University of
Grenoble (INPG), Design & Reuse
DSP TECHNOLOGY - 99q2 - p. 20
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| TOOLS |
New Trends in Real-Time Software Debugging
Using test points for monitoring signals is a basic part
of hardware debugging. Continuously
collecting and visualizing signals in real time from
a working environment provides the foundation
for understanding the system’s behavior. Be it an electronic
board, a data network or even the human
body, the concept of monitoring a set of test points
in real-time is the essence of trouble-shooting.
SurroundView is a new software development tool, which
facilitates the instrumentation of real time
software applications with test points. It perform its
tasks utilizing an agent-host architecture.
SurroundView provides a highly efficient method for adding
numerous monitoring test points within
a real time target application, utilizing these test
points to monitor, visualize and analyze the
application’s behavior while it is running.
By Eldad Maniv, Founder & CEO, RTView Ltd
DSP TECHNOLOGY - 99q2 - p. 23
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Speech Recognition at Lernout & Hauspie - An opportunity for
embedded systems
Lernout & Hauspie is a company focused on speech
and language technologies. Lernout & Hauspie
is the only company offering a full range of speech and
language technologies. Automatic Speech
Recognition or ASR and TTS or Text to Speech for automatic
text generation are the dual links
between text and speech. Speech compression or coding
algorithms are used when speech is sent
over a channel with limited bandwidth or has to be stored
on media with limited memory before it is
played back. Machine Translation, enhanced with human
translation whenever necessary, was the
missing link between text and text and has been integrated
in the company due to acquisitions in the
recent years.
By Eric Van Compernolle, Head of Basic Research Division,
Lernout & Hauspie
DSP TECHNOLOGY - 99q2 - p. 26
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Proposal for a system-on-a-chip model
With RISC architectures no longer being as reduced as
they used to be, CISC being build on top of
RISC principles, DSP embracing RISC as well as VLIW principles,
we see DSP capability being added
to almost any architecture. While on the desktop world,
this mostly means adding throughput capabili-
ties for compute intensive algorithms, in the embedded
world, the boundary conditions are more
restrictive. Besides the need to operate on high bandwidth,
low latency real-world data, the system
must often be low power, small size and often be as cheap
as possible. In addition, the applications
must cope with shortening times to market, reliability,
increasing complexity and flexibility to change
the runtime algorithms. These issues can be solved by
taking a software point of view based on multi-
tasking and resulting in very efficient but modular asynchronous
architectures.
By Eric Verhulst, Founder & CEO, Eonic Systems
NV
DSP TECHNOLOGY - 99q2 - p. 31
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Real-Time DSP applications benefit from high-level language compilation
Even today, software development for real-time applications
will often involve you in writing at least
part of your code in assembler to improve its execution
speed. This is particularly true for DSP proces-
sors, where hand-crafted assembly language programming
is still the norm rather than exception
when writing code for the tight loops at the heart of
many DSP algorithms. Standard C compilers, with
their lack of support for the fixed-point data types,
divided memory spaces, dedicated register sets
and circular buffers that typify most embedded DSP, are
unable to produce code that executes fast
enough. In addition, the high degree of instruction-level
parallelism inherent in the latest DSP architec-
tures poses considerable problems for compiler developers
because of the wide design space and
large number of code optimisation strategies involved.
However, with the introduction of a new version
of ACE's CoSy Compiler Development Platform, together
with proposed extensions to the C program-
ming language, this situation is changing rapidly.
By Marco Roodzandt, VP Marketing & Sales, ACE Associated
Compiler Experts bv
DSP TECHNOLOGY - 99q2 - p. 40
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Software for DSP comes of age
The use of programmable Digital Signal Processors (DSPs)
is central to many of today’s hot applica-
tion areas. The market forces operating in sectors such
as telecommunications mean that the window
of opportunity may only be open for a short time, and
delays in software development can threaten
viability of an entire project. To compound the problem,
DSP’s are becoming more sophisticated and
powerful with each new device announcement, a factor
that fuels increasing complexity in the appli-
cation software and thus increases risk. In circumstances
like this it is crucial that the software devel-
oper has the best possible tools to help in the application
development task. This article discusses
the range of development software available to the DSP
developer and covers some of the factors
influencing its evolution.
By By Nick Keeling,Product Manager,Blue Wave Systems
DSP TECHNOLOGY - 99q2 - p. 41
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| PROCESSOR |
Parallel FPGA Processor Card for Distributed Information Processing
This article presents an FPGA-based board, the
Parallel FPGA Processor Card PFPC-1V, designed for real-time DSP applications.
The board is intended for operating as a hardware accelerator in conjunction
with general purpose main processor on VME bus. PFPC-1V includes 1 RISC-like
control unit and 6 processing units implemented in ALTERA FLEX 10K, and
2 bidirectional link ports. Architectures of control and processing units
can be flexibly adapted to certain tasks, and for any particular architecture
appropriate software can be generated.
By Sergey I. Aryashev, Sergey G. Bobkov, Evgueni A.
Sidorov, Ilya V. Yudin, Institute for System Studies, Russian Academy of
Sciences (abbr. NIISI RAS)
DSP TECHNOLOGY - 99q2 - p. 46
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Baseband IC solutions address the fast changing subscriber handset
market
In today’s fast-paced, highly competitive world of wireless
communications, handset manufacturers
continually seek to gain an edge on the competition.
There are a number of ways to do this – make
phones that are cheaper, smaller, run longer on a single
battery charge, contain timesaving features
and offer secure communications. These are a few of the
traditional roads to product differentiation.
By Nick Marschall, Gary Silcott and Thierry Bailleul,
Wireless Subscriber Systems Group, Motorola
DSP TECHNOLOGY - 99q2 - p. 51
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Hyperstone E1-32X RISC/DSP Single-core RISC/DSP processors for low
cost embedded multimedia and internet enabling systems
The article describes the hyperstone unified RISC/DSP
processor architecture for embedded systems and DSP applications. High-volume
customers for hyperstone RISC/DSP processors are mainly in the area of
digital still cameras, fingerprint recognition systems, telecommunication,
hand-held Internet enabling devices. Peak per-formance of the hyperstone
E1-32X RISC/DSP is 80 MIPS and 240 million operations per second (MOPS).
Among others, the chips include an integrated memory of 8 kBytes, a bus
interface for glue-less con-nection of memory and periphery, and a PLL.
Power consumption of the hyperstone E1-32X is as low as 80 mW at 2.7 V
and 50 MHz.
By Matthias Steck, Director of marketing and sales,
Hyperstone Electronics
DSP TECHNOLOGY - 99q2 - p. 55
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General Purpose Processors for Foating-Point DSP
“DSP” is an application space and the set of microprocessors
which address the needs of those appli-
cations. When selecting a microprocessor there are four
key attributes that facilitate DSP performance.
First, the microprocessor must perform simple arithmetic
operations every clock cycle. Second, it must
be able get the data in and out of the processor in a
quick and controllable manner. Third, it must be
supported by a powerful development environment tailored
to real-time applications. And fourth, for
embedded DSP, it must optimize computational speed with
considerations to size, power, and cost
objectives.
By Steve Paavola, Product Manager, SKY Computers, Inc.
DSP TECHNOLOGY - 99q2 - p. 60
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The RISC challenge in DSP processing
A new wave of microprocessors is taking the lead in advanced
embedded computing offering
computational power for control as well as dedicated
DSP tasks. This new generation of processors
is based on the RISC design philosophy and challenge
traditionally separated controller and DSP
processor solutions.
By Dr. Manfred Schlett, Product Manager, Hitachi Europe
DSP TECHNOLOGY - 99q2 - p. 64
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TriCore 32-bit MCU/DSP - How to win both ways
One of the targets of the Infineon Tricore 32-bit unified
processor was to reach full-blown DSP perfor-
mance while keeping the software friendliness of a 32-bit
CPU. To reach that goal, all the DSP fea-
tures were carefully integrated in the architecture while
keeping a “software friendly” programming
environment. This lead to the Tricore architecture.
As shown in an a series of DSP benchmarks, the Tricore
results are similar to a Dual-Mac DSP, with
as a big advantage that the TriCore architecture is easier
to program and behaves much better on
common CPU algorithms.
By Daniel Martin, Senior DSP Architect, Infineon Technologies
DSP TECHNOLOGY - 99q2 - p. 70
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|
| OTHERS |
Book Review
DSP TECHNOLOGY - 99q2 - p. 74
Bookstores
DSP TECHNOLOGY - 99q2 - p. 75
Agenda
DSP TECHNOLOGY - 99q2 - p. 76
Company Directory
DSP TECHNOLOGY - 99q2 - p. 78
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DSP TECHNOLOGY - 99q2 - p. 80
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