Editorial 4Q96
RISCY Real-Time?
In the previous issue, you had the opportunity to fine-tune your knowledge about the research effort of the OMI programme and the practical consequences for industry. As the number of submissions was considerable, still some OMI contributions are discussed hereafter, particularly those on new chip developments as these are well-suited for this issue.
We had announced this issue as a "Chips" Issue. We had asked for papers on processors used in real-time applications and bus interface and bridge chips. We have received some very interesting papers about the PowerPC family and a description of the SPARClet, a new TEMIC processor intended for communication applications. However, most of the contributions describe VME and PCI bridges and bus interfaces. Hence why, I considered it more appropriate to name this issue "Bus Interfacing".
I hope this magazine will clear up the myth about the use of PowerPC chips in real-time applications. When I stated during my seminars that the 600 PPC is not a good processor for real-time systems, some people disagreed and pointed out the high performance of the processor. This shows once more the confusion that exists between real-time and being fast.In this magazine, we define that
real-time systems should respond in a timely predictable way to unpredictable external stimuli arrivals.
To satisfy this requirement you need of course a certain processor performance, though the processor and the system should be constructed so as to permit a predictable response initiated by interrupts (stemming from the external stimuli). The article by Geoff Revill, Managing Director at Software Development Systems, explains what the different processors in the PPC family are capable of and what you should do to make the machine respond in a predictable way. For each type of application, there is a processor in the family. As the PPC 600 series has only one interrupt line, it is more suitable for number crunching applications with a very limited amount of external stimuli. You should note his advice about some software exceptions with higher priorities than the hardware interrupts! The simple existence of the 400, 500 and 800 series shows that the 600 series is definitely not suited for all kind of real-time applications.
The choice is yours, but when you start a new project, do not reduce your "processor-to-be-used" decision to a formality. Price will certainly be an issue, but you cannot make a machine respond in a predictable way if you have unpredictable processor behaviour. Interrupt handling certainly deserves some attention here, as well as is the use of cache and pipe-lining techniques, introducing what could be called the "variable performance engine" concept. This is not necessarily what we need if you use Rate Monotonic Scheduling modelling, but this is a discussion for another issue. Stay tuned!